1. Technical Field of the Invention
The present invention relates to memory devices, and more particularly to a relatively fast and efficient word line decoder having a reduced number of transistors.
2. Description of the Related Art
Memory array devices, such as static RAM (random access memory) or ROM (read-only memory) devices or the like, require row and column address decoders to access the desired digital information (bits) of the memory array. The present disclosure primarily concerns the row or word line decoder for a memory device, although the techniques described herein are applicable to other decoding schemes. Single stage word line decoders using conventional complementary metal-oxide semiconductor (CMOS) decoding techniques require a substantial number of CMOS transistors to implement the decoder. Thus, single stage designs are limited to a small number of address lines and are not sufficient for practical designs having more address lines. Dual-stage word line decoders reduce the number of transistors required, but introduce significant delay for the two separate decoder stages.
If the number of address bits, referred to by the integer "n," is relatively small, such as n=4 or less, then word line decoding may be achieved in a single stage. For example, if n=4, then 2.sup.n =16 NAND gates are necessary to implement the word line decoder, where each NAND gate includes n=4 inputs. In the conventional design, a four-input NAND gate requires four P-channel transistors and four N-channel transistors for a total of 2(n)=8 transistors for each word line NAND gate. Thus, a total of 16.times.8=128 transistors are required for a four-bit word line decoder.
It is easy to see that as the number of address lines increases, the number of transistors required to implement a conventional single stage decoder becomes excessive. For example, for nine address lines, over 9,000 such CMOS transistors are required, just for the word line decoder alone. Such single-stage implementations become too large and costly for practical purposes.
Furthermore, since each decoding gate is typically implemented using a stack of series connected N-channel transistors, a practical limit exists on the number of inputs or width of each decoding gate. The resistance of the stack increases with each added N-channel transistor, where the total resistance becomes excessive very quickly. Since the output capacitance is generally fixed, each added transistor resistance increases the switching time of the gate, which correspondingly slows down the memory device itself One way to reduce the series resistance is to increase the size or the width/length (w/l) ratio of each transistor. This is undesirable because it correspondingly increases the size of the transistor, and thus the size of the overall memory device. For these reasons, single stage decoders using conventional CMOS technology is typically limited to a small number of address lines, such as four or less.
One way to reduce the number of transistors is the use of pre-charging techniques where only one P-channel device is required This effectively reduces the number of overall transistors by half for the overall single-stage decoder. However, the N-channel devices are still stacked in series and the pre-charging technique requires an additional N-channel device to be added to file stack. In this manner, such pre-charging techniques do not completely solve the practical address line limit of single stage decoders.
For the reasons listed above, designers have used two-stage decoders which include a predecoder stage and a postdecoder stage. The address lines are effectively grouped and provided to predecoder stages for developing a predecoder bus. For example, four address lines are divided into two groups of two, where each group of two is provided to a corresponding 2:4 decoder to create an eight-bit predecoder bus. Likewise, nine address lines are divided into three groups of three address lines, where each group of three is provided into a corresponding 3:8 decoder for developing a 24-bit predecoder bus, and so on. The use of two stages reduces the number of inputs required for each gate in the postdecoder stage to the number of decoders in the predecoder stage. In this manner, the postdecoder stage uses sixteen, two-input word line gates for four address lines, or 512 three-input word line gates for nine address lines. It is clear, therefore, that the use of predecoder and postdecoder stages substantially reduces the number of transistors required to implement the overall word line decoder. However, the introduction of two separate stages effectively doubles the time required to complete the word line decode process.
It is desired to provide an improved word line decoder which is very fast, yet implemented with a relatively small number of transistors.